Pulse pile-up rejector with live-time corrector circuit

ABSTRACT

A live-time corrector circuit is provided in an x-ray counting device wherein the dead time of the analyzer device as well as dead time caused by overlapping events are compensated for by extending the counting time.

United States Patent [191 Lewes June 4, 1974 PULSE PlLE-UP REJECTOR WITH3,382.365 5/1968 Lacour et ill 250/83.6 R 3.571639 4/1971 Metz et a].250/83.6 R x LIVE-TIME CORRECTOR CIRCUIT [75] Inventor: Albert RobertLowes, Burlingame,

Primary ExaminerArchie R. Borchelt [73] Assignee: Kevex Corporation,Burlingame,

Calif.

[22] Filed: Apr. 24, 1972 [21] Appl. No.: 246,819 ABSTRACT 52 us. Cl.250/336, 250/374 7 A live-time Corrector circuit is Provided an may 511im. Cl. G0lt 1/00 Counting device wherein the dead time Of the analyzer[58] Field of Search 250/83.6 R, 336, 374 device as as dead time Causedby Overlapping events are compensated for by extending the counting [56]References Cited UNITED STATES PATENTS 3.037.118 5/1962 Bryant 250/83.6R 2 Claims, 1 Drawing Figure FAST AMP 7 u 12 I? To ,1 .n. DRATE- CIRCUITPULSE PlLE-UP REJE$TlON----- CONTROL LOGIC PULSE PILE-UP REJECTOR WITHLIVE-TIME CORRECTOR CIRCUIT SUMMARY OF THE INVENTION In the analysis ofx-ray events by electronic instrumentation, a detector and itsassociated circuitry are looking for x-ray events which occur randomlyin time. Modern high resolution x-ray energy analysis units require thatthe amplifier must be set for a time constant of or 6 microseconds.Since the number of expected counts mayrun into the thousands of countsper second, the long duration of the resultant pulses greatly increasesthe chance of pile-ups, resulting in the data recorded in the pulseheight analyzer being stored in the incorrect channel, thus reducing theheight of peaks and increasing the general background noise. In otherwords, when an event occurs, a finite time is required to process thesignal and, if during this time 'a subsequent event occurs, the twosignals tend to add or be superimposed on each other. This creates afalse signal whose value does not correlate with either of the componentsignals and which must be disregarded in the analysis. Many electronicschemes have been suggested to prevent the analysis of erroneous signalsand the generic term pulse pile-up rejection circuitry" is common in theindustry. The usual process is to examine theevents in two channels, onea fast channel which barely detects the occurance of the event and theother a slower channel which may properly process and analyze thesignal. In such circuits if a second event occurs during the time whenthe first event is being processed, the rejection circuitry rejects bothsignals. Further, during the analysis period in a multiple channelanalyzer, no new signals can be accepted for processing. Both of thesesituations, i.e., two signals arriving so close together than onedistorts the other or a second signal arriving while the first signal isbeing processed, result in dead time.

It is normally desirable to determine the activity of certain eventsduring a definite time period and these results will vary as thelive-time to dead time ratio changes. If the system is dead half thetime, obviously only about half of the events occuring during the runare being processed.

In accordance with the present invention, this situation is corrected byinhibiting the clock which governs the counting time during the deadtime period. In other words, if one wishes to analyze the events of aperiod such as one minute and the system is dead half the time, the realrunning time will be two minutes and during this period the actual countis taking place for one min- Ulti.

BRIEF DESCRIPTION OF THE DRAWINGS The sole FIGURE of the drawing is aschematic diagram of an apparatus embodying the present invention.

DESCRIPTION OF THE PREFERRRED EMBODIMENT ferentiate the signal with ashort time constant (suitably 200 ns) and it is then fed to a one-shotmultivibrator 7 which puts out a constant amplitude pulse ofapproximately 1 to 2 microseconds each time an event occurs. The outputfrom the fast discriminator is fed to an NAND gate 9, the output ofwhich is fed to a second one-shot multivibrator 11 having Q and Qoutputs which are fed to the NAND gates 13 and 15. The time constant ofmultivibrator 11 is selected to match the full pulse width of thequasi-Gaussian shaped main linear pulse for any particular shapingtime-constant and is suitably 10 times the slow amplifier time constant.The output from the NAND gates 13 and 15 is then fed to the set andreset gates respectively of the flip-flop 17. Output is taken fromflip-flop l7'from the Q output through line 19 and served to actuate thelinear gate, later described. It will be seen that enable line 19 willbe actuated by a pulse from the fast discriminator unless it isinhibited by a pulse from the one-shot multivibrator 11. Should a secondpulse occur during the offtime of 11, no enabling pulse will be sentthrough line 19. In other words, if the pulses are sufficiently farapart that they can be properly processed, enable line 19 will beactivated, while if two pulses occur too close together to be properlyprocessed, line 19 will not be activated.

As was previously mentioned, the signal from the preamplifier at l issplit in two parts and the second portion goes to the slow or mainamplifier 5. The latter will now be described. In the slow amplifier 5and the pulse stretcher, generally designated 21, the pulse 'isamplified and stretched to 2 microseconds and the peak of the signal isdetected. The peak signal is then passed to the linear gate generallydesignated 23 and, if the gate is opened by a pulse through line 19, is

passed through voltage follower 25 into a multichannel analyzer 27. Theexact method of stretching the pulse, detecting the peak and analyzingit in the analyzer 27 is known to those skilled in the art and thereforehas not been described in detail.

Each time an event occurs the fast amplifier pulse is also fed to theset terminal of flip-flop 29. The apparatus is provided with a clockoscillato r 31 and the output from the clock oscillator and the Q outputfrom flipflop 29 are fed to AND gate 33. The output from AND gate 33goes to a counter-timer 35 where the number of clock pulses is countedand the operation cut off after the desired time interval. Thus, as apulse is received at the S terminal of flip-flop 29, the output of theclogk 31 is shut off since AND gate '33 is connected to the Q output offlip-flop 29.

A second AND gate 37 has its output connected to the reset terminal ofslip-flop 29 and one of the inputs of AND gate 37 is connected throughline 39 to the multichannel analyzer which puts out a pulse if theanalyzer is not busy processing asignal. The other input to AND gate 37is through line 41 and everytime the linear gate 23 is opened to theanalyzer 27, line 41 is pulsed. This will operate the reset of flip-flop29 providing that the multichannel analyzer is not bus and has put out asignal through line 39. This gives a goutput on flip-flop 29 so that theclock pulses 31 are fed into the counter-timer 35.

The overall operation of the circuit will now be apparent. Each time apulse is received, flip-flop 29 will go to the set condition and thelive-time counter 35 will be turned off. Simultaneously the pulse willbe processed through the slow amplifier side of the circuit and thelinear gate 23 will be opened by a pulse from line 19 unless two pulsesoccur close together. When the gate 23 is opened, the pulse is sent tothe multichannel analyzer 27 for processing and, if the analyzer is notbusy, an output pulse from line 39 will be added to that of line 41,resetting flip-flop 29 causing the clock pulses to be accumulated in 35.

The design philosophy of this circuit is extremely simple. For a givencount rate, the average period between event is n T= 2 T.-=1/count ratewhere T,- is the actual time between events i and i-H. Therefore,although T, varies from event to event, the statistical average over along period of time is given by the inverse of the count rate. Inoperation, the live-time counter 35 is enabled only if an event isstored in the analyzer and is again disabled at the next event. If thenext event is also stored, the clock is again enabled for one eventperiod, T,. Therefore, for each event stored, the clock. runs for aperiod T,. If the count rate is 5,000 counts per second, then T= l/5,00Qseconds. lfa livetime of 100 seconds is desired, there will be 500,000counts stored on the average but the actual real time required toaccumulate these counts will be 100 x 100/100 70 dead time].

lt will be obvious to those skilled in the art that many variations canbe made without departing from the spirit of this invention.

1 claim:

1. In an analyzer for x-ray events wherein the amplitude and number ofevents are recorded in a multichannel analyzer and said events may occurat a rate faster than the events can be processed by said multichannelanalyzer, because said analyzer exhibits dead time during processing,the improvement comprising:

a. an input circuit from the pre-amplifier of an x-ray event detectorproviding a series of pulses,

b. means for dividing the pulses from said input circuit into twoparallel paths,

c. the first of said paths being a fast channel which detects pulses,

d. the second of said paths being a slow channel to said multichannelanalyzer which processes and gates pulses,

e. a live-time clock for determining the live time period during which aseries of counts is made,

f. means whereby said fast circuit actuates a pulse pile-up rejectioncircuit having means which stops said live-time clock when two pulsesare in such close proximity that they cannot be analyzed by saidmultichannel analyzer, and

g. a second circuit actuated by said multichannel analyzer which shutsoff said live-time clock when said multichannel analyzer is busy.

2. The analyzer of claim 1 including the following structure:

a. a pulse pile-up rejection circuit in said fast channel, said circuithaving means for opening a linear gate in said slow channel in theabsence of overlapping Pulses,

b. said fast channel having means for stopping said live-time clock aseach pulse is received,

0. said slow channel shaping and passing pulses to a multiple channelrecorder,

(1. said slow channel actuating one input of an AND gate when a pulse isprocessed, e. said multichannel recorder having means to send a not busysignal to the other input of said AND gate when not processing a signal,and

f. the output of said AND gate causing said live-time cloektorun.

1. In an analyzer for x-ray events wherein the amplitude and number ofevents are recorded in a multichannel analyzer and said events may occurat a rate faster than the events can be processed by said multichannelanalyzer, because said analyzer exhibits dead time during processing,the improvement comprising: a. an input circuit from the pre-amplifierof an x-ray event detector providing a series of pulses, b. means fordividing the pulses from said input circuit into two parallel paths, c.the first of said paths being a fast channel which detects pulses, d.the second of said paths being a slow channel to said multichannelanalyzer which processes and gates pulses, e. a live-time clock fordetermining the live time period during which a series of counts ismade, f. means whereby said fast circuit actuates a pulse pile-uprejection circuit having means which stops said live-time clock when twopulses are in such close proximity that they cannot be analyzed by saidmultichannel analyzer, and g. a second circuit actuated by saidmultichannel analyzer which shuts off said live-time clock when saidmultichannel analyzer is busy.
 2. The analyzer of claim 1 including thefollowing structure: a. a pulse pile-up rejection circuit in said fastchannel, said circuit having means for opening a linear gate in saidslow channel in the absence of overlapping pulses, b. said fast channelhaving means for stopping said live-time clock as each pulse isreceived, c. said slow channel shaping and passing pulses to a multiplechannel recorder, d. said slow channel actuating one input of an ANDgate when a pulse is processed, e. said multichannel recorder havingmeans to send a not busy signal to the other input of said AND gate whennot processing a signal, and f. the output of said AND gate causing saidlive-time clock to run.